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d a t a sh eet product speci?cation file under integrated circuits, ic02 1997 nov 12 integrated circuits TDA9851 i 2 c-bus controlled economic btsc stereo decoder
1997 nov 12 2 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 features voltage controlled amplifier (vca) noise reduction circuit stereo or mono selectable at the af outputs stereo pilot pll circuit with ceramic resonator automatic pilot cancellation automatic volume level (avl) control (+6 to - 15 db) i 2 c-bus transceiver. general description the TDA9851 is a bipolar-integrated btsc stereo decoder for application in tv sets, vcrs and multimedia pcs. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cc supply voltage 8 9 9.5 v i cc supply current - 30 40 ma v o(rms) output voltage (rms value) composite input voltage 250 mv (rms) for 100% modulation l + r (25 khz deviation); f mod = 300 hz - 500 - mv a csl,r stereo channel separation l and r 14% modulation; f l = 300 hz; f r = 3 khz - 20 - db thd l,r total harmonic distortion l and r 100% modulation l or r; f mod = 1 khz - 0.2 1.0 % s/n signal-to-noise ratio mono mode; referenced to 500 mv output signal ccir 468-2 weighted; quasi peak 50 60 - db din noise weighting filter (rms value) - 73 - dba type number package name description version TDA9851 sdip24 plastic shrink dual in-line package; 24 leads (400 mil) sot234-1 TDA9851t so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1997 nov 12 3 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 block diagram b ook, full pagewidth mha969 stereo decoder dematrix and mode select automatic volume level detector and voltage controlled amplifier supply filter and reference i 2 c-bus transceiver TDA9851 l - r l + r 89 c5 q1 c6 c10 c11 c13 c mo 3 c4 c3 c2 r1 c ph 4 cer 5 c p1 6 c p2 c ss 16 11 n.c. c7 c av 12 13 24 1 sda scl outl outr c1 composite baseband input 7 comp 21 fdi 20 fdo r3 c9 r2 19 18 17 bpu c w tw c14 21522 c15 14 v cc v cap agnd v ref 23 dgnd r4 10 r fr fig.1 block diagram.
1997 nov 12 4 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 component list electrolytic capacitors 20%; foil capacitors 10%; resistors 5%; unless otherwise speci?ed; see fig.1. component value type remark c1 2.2 m f electrolytic 63 v c2 220 nf foil c3 2.2 m f electrolytic 63 v c4 220 nf foil c5 2.2 m f electrolytic 63 v c6 2.2 m f electrolytic 63 v c7 4.7 m f electrolytic 63 v 10% c9 22 nf foil c10 4.7 nf foil c11 1 m f electrolytic 63 v c13 10 m f electrolytic 63 v c14 100 m f electrolytic 16 v c15 100 m f electrolytic 16 v r1 3.3 k w r2 15 k w r3 1.3 k w r4 100 k w q1 csb503f58 radial leads csb503jf958 alternative as smd
1997 nov 12 5 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 pinning symbol pin description scl 1 serial clock input (i 2 c-bus) v cc 2 supply voltage c ph 3 capacitor for phase detector cer 4 ceramic resonator c p1 5 capacitor for pilot detector c p2 6 capacitor for pilot detector comp 7 composite input signal c mo 8 capacitor dc-decoupling mono c ss 9 capacitor dc-decoupling stereo r fr 10 resistor for ?lter reference n.c. 11 not connected outl 12 output, left channel outr 13 output, right channel v ref 14 reference voltage 0.5v cc v cap 15 capacitor for electronic ?ltering of supply c av 16 automatic volume control capacitor tw 17 capacitor timing c w 18 capacitor for vca and band-pass ?lter lower corner frequency bpu 19 band-pass ?lter upper corner frequency fdo 20 ?xed de-emphasis output fdi 21 ?xed de-emphasis input agnd 22 analog ground dgnd 23 digital ground sda 24 serial data input/output (i 2 c-bus) fig.2 pin configuration. handbook, halfpage scl v cc c ph cer c p1 c p2 comp c mo c ss r fr n.c. outl sda dgnd agnd fdi bpu c w fdo tw c av v cap v ref outr 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 TDA9851 mha968
1997 nov 12 6 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 functional description stereo decoder the composite signal is fed into a pilot detector/pilot cancellation circuit and into the mpx demodulator. the main l + r signal passes a 75 m s fixed de-emphasis filter and is fed into the dematrix circuit. the decoded sub-signal l - r is sent to the vca circuit. to generate the pilot signal the stereo demodulator uses a pll circuit including a ceramic resonator. mode selection the l - r signal is fed via the internal vca circuit to the dematrix/switching circuit. mode selection is achieved via the i 2 c-bus. automatic volume level control the automatic volume level stage controls its output voltage to a constant level of typically 200 mv (rms) from an input voltage range between 0.1 to 1.1 v (rms). the circuit adjusts variations in modulation during broadcasting and because of changes in the programme material. the function can be switched off. to avoid audible plops during the permanent operation of the avl circuit a soft blending scheme has been applied between the different gain stages. a capacitor (4.7 m f) at pin c av determines the attack and decay time constants. in addition the ratio of attack and decay times can be changed via the i 2 c-bus. integrated ?lters the filter functions necessary for stereo demodulation are provided on-chip using transconductor circuits. the filter frequencies are controlled by the filter reference circuit via the external resistor r4. limiting values in accordance with the absolute maximum rating system (iec 134). note 1. machine model class b. thermal characteristics symbol parameter conditions min. max. unit v cc supply voltage 0 9.9 v v sda , v scl voltage of sda and scl to gnd v cc <9v 0 v cc v v cc 3 9v09v v n voltage of all other pins to gnd 0 v cc v t amb operating ambient temperature t j < 125 c - 20 +70 c t stg storage temperature - 65 +150 c v es electrostatic handling note 1 -- v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air TDA9851 (sot234-1; sdip24) 55 k/w TDA9851t (sot137-1; so24) 90 k/w
1997 nov 12 7 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 characteristics all voltages are measured relative to gnd; v cc =9v; r s = 600 w ; ac-coupled; r l =10k w ; c l = 2.5 nf; f mod = 1 khz mono signal; composite input voltage 250 mv (rms) for 100% modulation l + r (25 khz deviation); t amb =25 c; see fig.1; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cc supply voltage 8 9 9.5 v i cc supply current - 30 40 ma input stage v i(max)(rms) maximum input voltage (rms value) 2 -- v z i input impedance 20 25 30 k w stereo decoder hr headroom for l + r, l and r f mod = 300 hz; thd < 15% 9 -- db v pil(rms) nominal stereo pilot voltage (rms value) - 50 - mv v th(on)(rms) pilot threshold voltage stereo on (rms value) -- 35 mv v th(off)(rms) pilot threshold voltage stereo off (rms value) 15 -- mv hys hysteresis - 2.5 - db v o(rms) output voltage (rms value) 100% modulation l + r; f mod = 300 hz - 500 - mv a csl,r stereo channel separation l and r 14% modulation; f l = 300 hz; f r = 3 khz - 20 - db thd l,r total harmonic distortion l and r 100% modulation l or r; f mod = 1 khz - 0.2 1.0 % s/n signal-to-noise ratio mono mode; referenced to 500 mv output signal ccir 468-2 weighted; quasi peak 50 60 - db din noise weighting filter (rms value) - 73 - dba stereo decoder, oscillator (vcxo); note 1 f o nominal vcxo output frequency (32f h ) with nominal ceramic resonator - 503.5 - khz d f fr spread of free-running frequency with nominal ceramic resonator 500.0 - 507.0 khz d f cr capture range frequency nominal pilot 190 265 - hz
1997 nov 12 8 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 outputs outl and outr z o output impedance - 80 120 w v o dc output voltage 0.45v cc 0.5v cc 0.55v cc v r l output load resistance (ac-coupled) 5 -- k w c l output load capacitance -- 2.5 nf a ct crosstalk sap into l and r 100% modulation; f mod = 1 khz; sap; mode selector switched to stereo 50 70 - db vca i s nominal timing current for nominal release rate of vca detector i s can be measured at pin tw via current meter connected to 0.5v cc +1v 6.5 8 9.5 m a rel rate nominal detector release rate nominal timing current and external capacitor values - 125 - db/s automatic volume level control g v voltage gain maximum boost; note 2 5 6 7 db maximum attenuation; note 2 14 15 16 db g step equivalent step width between the input stages (soft switching system) - 1.5 - db v iop(rms) input voltage (rms value) maximum boost; note 2 - 0.1 - v maximum attenuation; note 2 - 1.125 - v v o(rms) output voltage in avl operation (rms value) 160 200 250 mv v offset(dc) dc offset voltage between different gain steps voltage at pin c av 7.0 to 6.83 v or 6.83 to 6.61 v or 6.61 to 5.83 v or 5.83 to 3.1 v; note 3 -- 20 mv r att discharge resistors for attack time constant at1 = 0; at2 = 0; note 4 340 420 520 w at1 = 1; at2 = 0; note 4 590 730 910 w at1 = 0; at2 = 1; note 4 0.96 1.2 1.5 k w at1 = 1; at2 = 1; note 4 1.7 2.1 2.6 k w i dec charge current for decay time normal mode; ccd = 0; note 5 1.6 2.0 2.4 m a power- on speed-up; ccd = 1; note 5 - 30 -m a muting at power supply voltage drop for outr and outl d v cc supply voltage drop for mute active - v cap - 0.7 - v symbol parameter conditions min. typ. max. unit
1997 nov 12 9 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 notes to the characteristics 1. the oscillator is designed to operate together with murata resonator csb503f58 or csb503jf958 as smd. change of the resonator supplier is possible, but the resonator speci?cation must be close to the speci?ed ones. 2. the avl input voltage is internal. it corresponds to the output voltage outl and outr at avl off. 3. the listed pin voltage corresponds with typical gain steps of +6 db, +3 db, 0 db, - 6 db and - 15 db. 4. attack time constant = c cav r att . 5. example: c cav = 4.7 m f; i dec =2 m a; g 1 = - 9 db; g 2 =+6db ? decay time results in 4.14 s. 6. when reset is active the gmu bit (mute) is set and the i 2 c-bus receiver is in the reset position. 7. the ac characteristics are in accordance with the i 2 c-bus specification for standard mode (clock frequency maximum 100 khz). a higher frequency, up to 280 khz, can be used if all clock and data times are interpolated between standard mode (100 khz) and fast mode (400 khz) in accordance with the i 2 c-bus specification. information about the i 2 c-bus can be found in brochure i 2 c-bus and how to use it (order number 9398 393 40011). power-on reset; note 6 v por(start) start of reset voltage increasing supply voltage -- 2.5 v decreasing supply voltage 4.2 5 5.8 v v por(end) end of reset voltage increasing supply voltage 5.2 6 6.8 v digital part (i 2 c-bus pins); note 7 v ih high-level input voltage 3 - v cc 9v v il low-level input voltage - 0.3 - +1.5 v i ih high-level input current - 10 - +10 m a i il low-level input current - 10 - +10 m a v ol low-level output voltage i il =3ma -- 0.4 v symbol parameter conditions min. typ. max. unit decay time c cav 0.76 v 10 g 1 C 20 ---------- 10 g 2 C 20 ---------- C ? ? ? ?? i dec ---------------------------------------------------------------------------------- =
1997 nov 12 10 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 i 2 c-bus protocol i 2 c-bus format to read (slave transmits data) table 1 explanation of i 2 c-bus format to read (slave transmits data) table 2 de?nition of the transmitted bytes after read condition table 3 function of the bits in table 2 i 2 c-bus format to write (slave receives data) table 4 explanation of i 2 c-bus format to write (slave receives data) table 5 de?nition of the data (second byte after mad) s slave address r/ w a data p name description s start condition; generated by the master standard slave address (mad) 101 101 1 r/ w logic 1 (read); generated by the master a acknowledge; generated by the slave data slave transmits an 8-bit data word p stop condition; generated by the master msb lsb d7 d6 d5 d4 d3 d2 d1 d0 yyyyyyystp bits function stp stereo pilot identification (stereo received = 1) y indefinite s slave address r/ w a data a p name description s start condition standard slave address (mad) 101 101 1 r/ w logic 0 (write) a acknowledge; generated by the slave data see table 5 p stop condition msb lsb d7 d6 d5 d4 d3 d2 d1 d0 0 0 at2 at1 ccd avlon gmu stereo
1997 nov 12 11 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 table 6 function of the bits in table 5 table 7 mode setting table 8 mute setting bits function stereo mode selection stereo or mono gmu mute control outl and outr avlon avl on/off ccd increased avl decay current on/off at1 and at2 attack time at avl function mode readable bit stp setting bit stereo outl outr left right 1 (stereo received) 1 mono mono 1 (stereo received) 0 mono mono 0 (no stereo received) 1 mono mono 0 (no stereo received) 0 function data gmu forced mute at outr and outl 1 no forced mute at outr and outl 0 table 9 avlon bit setting table 10 ccd bit setting table 11 avl attack time function data automatic volume control on 1 automatic volume control off 0 function data load current for normal avl decay time 0 increased load current 1 r att ( w ) data at1 at2 420 0 0 730 1 0 1200 0 1 2100 1 1
1997 nov 12 12 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 internal pin configurations fig.3 pin 1; scl. mha971 1 1.8 k w fig.4 pin 2; v cc . mha972 2 + fig.5 pin 3; c ph . mha973 3 10 k w 10 k w + fig.6 pin 4; cer. mha974 4 3 k w + fig.7 pin 5; c p1 . mha975 5 3.5 k w + fig.8 pin 6; c p2 . mha976 6 + 8.5 k w 12 k w
1997 nov 12 13 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 fig.9 pin 7; comp. mha977 7 + 25 k w 25 k w 25 k w 50 pf 100 pf fig.10 pin 8; c mo and pin 9; c ss . mha978 8, 9 10 k w 10 k w + fig.11 pin 10; r fr . mha979 10 1 k w + fig.12 pin 12; outl and pin 13; outr. mha980 12, 13 + 80 w fig.13 pin 14; v ref . mha981 14 3.4 k w 3.4 k w fig.14 pin 15; v cap. mha982 15 4.7 k w 300 w 5 k w +
1997 nov 12 14 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 fig.15 pin 16; c av . mha983 16 + fig.16 pin 17; tw. mha984 17 + fig.17 pin 18; c w . mha985 18 6 k w + fig.18 pin 19; bpu and pin 21; fdi. mha986 21 19 16 k w + + fig.19 pin 20; fdo. mha987 20 + fig.20 pin 24; sda. mha988 24 1.8 k w
1997 nov 12 15 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 application information fig.21 application circuit. handbook, full pagewidth mha970 c9 c10 c11 c13 c7 c14 c15 r3 r2 c3 c2 q1 c4 c1 c5 c6 r1 r4 v cc scl sda composite baseband input TDA9851 sda dgnd agnd fdi fdo bpu c w tw c av v cap v ref outr scl c ph cer c p1 c p2 comp c mo c ss r fr n.c. outl 24 23 22 21 20 19 18 17 16 15 14 13 12 3456789101112
1997 nov 12 16 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot234-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip24: plastic shrink dual in-line package; 24 leads (400 mil) sot234-1
1997 nov 12 17 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013ad pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 95-01-24 97-05-22
1997 nov 12 18 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). sdip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 nov 12 19 philips semiconductors product speci?cation i 2 c-bus controlled economic btsc stereo decoder TDA9851 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca55 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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